The Thematic Center for Quantum Computing, operating under the Research Center for Critical Issues at Academia Sinica, unveiled Taiwan’s first domestically developed five-qubit superconducting quantum computer last year. This article presents an overview of the Center’s current technological capabilities and outlines its strategic roadmap for future development.
The Center’s long‑term objective is to establish a superconducting quantum computing system characterized by high coherence, high fidelity, and strong scalability. The development of the five‑qubit system serves not only as a practical testbed for the integrated design, fabrication, and measurement of quantum chips, but also as a foundational step toward larger‑scale quantum
processors. To date, the research program has progressed from single‑qubit and coupled two‑qubit devices to the design and validation of coupled five‑qubit chips. Looking ahead, the Center plans to further expand its efforts toward multi‑qubit chip design and fabrication, system‑level integration, and the development of control software. As illustrated in the system architecture, the overall R&D framework is organized in a modular structure encompassing chip design, process development, and measurement and control systems. The measurement and control systems are further divided into system‑level hardware architecture and control software development. Ultimately, the platform will provide a comprehensive user interface that supports the development andexecution of a wide range of quantum algorithms and applications.
To strengthen domestic quantum hardware R&D capacity, Academia Sinica has established two key platforms at its Southern Campus (Shalun) within the Critical Infrastructure Building: the Quantum Chip Fabrication Space (QC-Fab) and the Quantum Computing Test Space (QC-Test). QC‑Fab provides commissioned fabrication services for quantum chips, while QC‑Test supports an integrated testing environment spanning hardware drive systems through upper‑layer control. Through an open platform architecture, the Center aims to collaborate with domestic and international partners to jointly advance the
development and validation of quantum computer hardware and the associated software stack. An overview video of the platforms is available for reference:
Chip Design Overview
During the design phase, initial efforts focused on the development of single‑qubit and coupled two‑qubit devices, with systematic evaluation of different qubit architectures and coupling strategies. These included comparisons between tunable‑frequency and fixed‑frequency designs, grounded and floating configurations, as well as Transmon and Fluxonium qubits. Through comprehensive measurement and performance assessment, optimal parameter configurations were identified. Building on these results, Academia Sinica subsequently fabricated five‑qubit quantum chips and conducted detailed analysis and optimization of crosstalk induced by flux and radio-frequency signals, thereby ensuring compatibility with logical gate operations.
By comparing qubit T1 relaxation times in isolated configurations and within five‑qubit chips, the research team assessed the impact of design choices on coherence performance. The five‑qubit architecture also serves as a validation platform for the design of key components, including couplers, resonators, Purcell filters, readout lines, microwave lines, and flux‑bias lines. In preparation for future system scaling, multi‑qubit chip design has already commenced, with a focus on flip-chip upper- and lower-layer layouts, signal routing, and the configuration and reliability analysis of through-silicon vias (TSVs).
Process Development Overview
In the domain of process development, initial efforts focused on analyzing the T1 relaxation times of single-qubit chips to identify and optimize critical fabrication steps affecting device stability. In parallel, cleaning techniques targeting metal surface contamination and dielectric removal were established.
With respect to Josephson junctions, extensive fabrication and characterization were conducted to identify key factors influencing junction resistance. Based on these findings, laser-based and current-based techniques were developed for the fine-tuning of junction resistance. To support multi‑qubit chip requirements, Academia Sinica optimized airbridge fabrication processes, thereby improving interlayer connectivity and structural reliability. In addition, quantum fabrication processes compatible with flip‑chip packaging have been implemented, alongside continued advances in stable through‑silicon via (TSV) processes to meet the vertical interconnection demands of large‑scale quantum systems.
System Hardware Architecture Overview
In terms of hardware integration, a chip enclosure providing electromagnetic and thermal shielding has been designed to support the installation and operation of quantum chips. This enclosure is complemented by a dedicated routing scheme for both cryogenic and room-temperature coaxial lines. Signal delay and distortion effects in printed circuit boards have also been carefully considered to ensure operational stability. The signal readout chain integrates parametric amplifiers and low-noise amplifiers (LNAs), precisely matched to resonator frequencies to achieve optimal readout performance. In parallel, plans are underway to introduce CryoCMOS (cryogenic CMOS) control and readout chip technologies, further enhancing measurement efficiency and control precision.
Status of Control Systems and Software Development
The design of quantum state readout and gate-control signals constitutes a core capability that directly determines quantum chip performance. Initial efforts focused on optimizing qubit state discrimination and readout mechanisms to improve accuracy. Subsequently, various single-qubit and two-qubit gate drive signals, including microwave and magnetic-field controls, have been developed and refined to achieve faster gate operations and higher fidelity. Multiple gate fidelity benchmarking tools have been established to serve as key indicators for improving subsequent algorithm performance and chip capabilities.
For multi‑qubit systems, Academia Sinica is developing gate programs that support multi-qubit entanglement operations, including Greenberger–Horne–Zeilinger (GHZ) state, as well as repetition-code encoding and decoding mechanisms. To meet practical operational requirements, automated procedures for gate operation and calibration are being implemented. In parallel, GPU computing resources are being utilized for cross‑entropy benchmarking (XEB) and digital twin simulations. Looking ahead, plans are underway to establish a hybrid classical–quantum computing platform to support applications such as variational quantum eigen solvers (VQE), the quantum approximate optimization algorithm (QAOA), quantum machine learning (QML), and quantum error correction (QEC).
Conclusion
The Thematic Center for Quantum Computing is committed not only to near-term chip fabrication and testing, but also to the medium- and long-term advancement of large-scale quantum systems and application-oriented development. Through the QC‑Fab and QC‑Test platforms, the Center will continue to work closely with domestic and international academic institutions and industry partners to progressively build an internationally competitive foundation for quantum hardware research and development and industrialization, thereby establishing a critical strategic advantage for Taiwan in the field of quantum technologies.
